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? 2003 microchip technology inc. ds40232h-page 1 MCRF450/451/452/455 features contactless read and wr ite with anti-collision algorithm 1024 bits (32 blocks) of total memory 928 bits (29 blocks) of user programmable memory unique 32-bit tag id (factory programmed) 32 bits for data and 16 bits for crc per block block write protection 70 kbit/s read data rate (manchester format) special bit (fast read) for fast identification and anti-counterfeit applications (eas) 1-of-16 ppm encoding for writing data interrogator-talks-first (i tf) or tag-talks-first (ttf) operation long range for reading and writing high-speed anti-collisio n algorithm for reading and writing fast and normal modes for write data speed anti-tearing feature for secure write transactions asynchronous operation for low power consumption and flexible choice of carrier frequency bands internal resonance capacitors (mcrf451/452/ 455) two pad connections for external antenna circuit (mcrf452) three pad connections for external antenna circuit (MCRF450, 451, 455) very low power cmos design die in waffle pack, wafer, wafer on frame, bumped wafer, cob, pdip or soic package options applications item level tagging: to read and write multiple items in long read range environment. anti-counterfeit: the device has a unique feature to distinguish between paid, unpaid or returned merchandise. inventory management: tag?s data can be read or updated (written) in multiple tags and long range environment. its memory (32 blocks, 1 kbit, each block = 32 bits) is well organized for the inventory management applications. product identification s airline baggage tracking book store and library book id low cost animal ear tags: the device?s long range reading performance combined with 1 kbit of memory is suitable fo r animal tagging applica- tions. tag cost can be cheaper and read range is much longer than existing 125 khz conventional animal ear tags. toys and gaming tools: device?s anti-collision feature for reading and writing allows to make intelligent interactive toys and gaming tools. access control and time attendance cards: device?s long ra nge performance allows to make long range access contro l, parking lot entry, and time attendance cards. inexpensive finished tags and readers are available from microchip?s worldwide oem partners. please contact microchip technology inc. near you or visit http://www.microchip.com for further product information and inquiries for your applications. typical configuration for applications command and data read/write data interrogator mcrf452 (reader/writer) ant. a v ss read/write range:~ up to 1.5 meters depending on tag size and system requirements. 13.56 mhz read/write passive rfid device
MCRF450/451/452/455 ds40232h-page 2 ? 2003 microchip technology inc. package types pdip (?p?) ant. a v dd 1 2 3 4 8 7 6 5 nc ant. b clk f clk nc v ss note: pins 4, 7 and 8 are for device test purposes only MCRF450/451/455: antenna connections = pins 1, 3 and 5 mcrf452: antenna connection s = pins 1 and 5 rotated soic (?x/sn?) ant.b v dd 1 2 3 4 8 7 6 5 nc clk f clk nc v ss note: pins 3, 5 and 7 are for device test purposes only MCRF450/451/455: antenna connections = pins 1, 4 and 8 mcrf452: antenna connections = pins 4 and 8 ant. a nc = not connected nc = not connected 5mm 8mm thickness = 0.4 mm antenna coil connection MCRF450 cob (?7m?)
? 2003 microchip technology inc. ds40232h-page 3 MCRF450/451/452/455 1.0 description of device features the MCRF450/451/452/455 is a contactless read/write passive rfid device that is optimized for 13.56 mhz rf carrier signal. the de vice needs an external lc resonant circuit to commun icate wirelessly with the interrogator. the device is powered remotely by rectifying an rf signal that is transmitted from the interrogator and transmits or updates its contents from memory-based on commands from the interrogator. the device is engineered to be used effectively for item level tagging applications, su ch as retail and inventory management, where a large vo lume of tags are read and written in the same interrogator field. the device contains 32 blocks (b0-b31) of eeprom memory. each block consists of 32 bits. the first three blocks (b0-b2) are allocated for device operation, while the remaining 29 blocks (b3- b31: 928 bits) are for user data. block 1 contains unique 32 bits of tag id. the tag id is preprogrammed at the factory and write protected. all blocks, except for the ta g id (block 1), are contact- lessly writable block-wise by interrogator commands. all data blocks, with the exce ption of bits 30 and 31 in block 0, are write-protectable. the device can be configured as either tag-talks-first (ttf) or interrogator-talks-first (itf). in ttf mode, the device transmits its fa st response data (160 bits max., see example 9-1) as so on as it is energized, then waits for the next command. in itf mode, the device requires an interrogator command before it sends any data. the control bits for ttf and itf modes are bits 30 and 31 in block 0. all downlink commands from the interrogator are encoded using 1-of-16 pulse position modulation (ppm) and specially timed gap pulses. this encoded information amplitude modul ates the interrogator?s rf carrier signal. at the other end, the MCRF450/451/452/455 device demodulates the received rf signal and then sends data (from memory) at 70 kbit/s back to the interrogator in manchester format. the communication between interrogator and device takes place asynchronously. therefore, to enhance the detection accuracy of the device, the interrogator sends a time reference signa l (time calibration pulse) to the device, followed by the command and program- ming data. the time re ference signal is used to calibrate timing of the inte rnal decoder of the device. there are device options for the internal resonant capacitor between antenna a and v ss : (a) no internal resonant capacitor for the MCRF450, (b) 100 pf for the mcrf451, (c) two 50 pf in series (25 pf in total) for the mcrf452 and (d) 50 pf for the mcrf455. the internal resonant capacitor s for each device are shown in figures 2-2 through 2-5. the MCRF450 needs an external lc resonant circuit connected between anten na a, antenna b and v ss pads. see figure 2-2 for the external circuit configura- tion. the mcrf452 needs a single external antenna coil only between antenna a and v ss pads, as shown in figure 2-4. this external circuit, along with the internal resonant capacitor, must be tuned to the carrier frequency of the interrogator for maximum performance. when a tag (device with th e external lc resonant circuit) is brought to the interrogator?s rf field, it develops an rf voltage across the external circuit. the device rectifies the rf voltage and develops a dc voltage (v dd ). the device becomes functional as soon as v dd reaches the operating voltage level. the device then sends data st ored in memory to the interrogator by turning on/off the internal modulation transistor. this internal modu lation transistor is located between antenna b and v ss . the modulation transistor has a very small turn-on resistance between drain (antenna b) and source (v ss ) terminals during its turn-on time. when the modulation transistor turns on, the resonant circuit component betw een antenna b and v ss , which is in parallel with the modula tion transistor, is shorted due to the low tu rn-on resistance. th is results in a change in the lc value of th e circuit. as a result, the circuit no longer resonates at the carrier frequency of the interrogator. therefore, the voltage across the circuit is minimized. this condition is called ?cloaking?. when the modulation transistor turns off, the circuit resonates at the carrier fr equency of the interrogator and develops maximum voltage. this condition is called ?uncloaking?. therefore, the data is sent to the interrogator by turning on (cloaking) and off (uncloaking) the modulation transistor. the voltage amplitude of th e carrier signal across the lc resonant circuit c hanges depending on the amplitude of modulation data . this is called an ampli- tude modulation signal. th e receiver channel in the interrogator detects this amplitude modulation signal and reconstructs the modul ation data for decoding. the device includes a unique anti-collision algorithm to be read or written effectively in multiple tag environ- ments. to minimize data co llision, the algorithm utilizes time division multiplexing of the device response. each device can communicate with the interrogator in a different time slot. the devi ces in the interrogator?s rf field remain in a nonmodulatin g condition if they are not in the given time slot. this enables the interrogator to communicate with the mult iple devices one at a time without data collision. the de tails of the algorithm are described in section 6.0 ?read/write anti-collision logic? .
MCRF450/451/452/455 ds40232h-page 4 ? 2003 microchip technology inc. to enhance data integrity for writing, the device includes an anti-tearing feature. this anti-tearing feature provides verification of data integrity for incomplete write cycles due to failed communication between the interrogator and the device during the write sequences. 1.1 device?s communication with interrogator the device can be operated in either fast read request (frr) or fast read bypass (frb) mode, depending on the status of bit 31 (fr: bit) of block 0. if the fr bit is set, the devi ce is operated in frr mode, and frb mode, if the fr bit is cleared. the fr bit is always reprogrammable and not write-protectable. the frr mode is a default setting. the communication between the interrogator and tag starts with a frr or frb command. in frr mode, the device sends a response only when it receives the frr command, not the frb command. conversely, the device in frb mode sends a response when it receives the frb command only, not the frr command. if the device is set to frr mode and also set to ttf mode (tf bit = set), the device can send the frr response as soon as it is energized. one of the main purposes of using the two different modes (frr and frb) is to use the device effectively in the item level supply-chai n application, where a rapid identification and an effe ctive anti-collision read/write process is needed (i.e., to identify whether it is a paid or unpaid item, or whether it passed one particular point of interest or not). this c an be done by either checking the status of the fr bit or by checking the response of the tag to the command. for this reason, the fr bit is also called an electronic art icle surveillance (eas) bit. 1.1.1 operation of tag in frr mode if the device is in the frr mode (fr bit = set), the communication between th e interrogator and the device can start in two ways, depending on the status of tf (bit 30 of block 0). if the tf bit is cleared, it is called itf mode. in this ca se, the tag waits for the interrogator?s frr comm and and sends the frr response data when it se es the frr command. if the tf bit is set, the device is in a ttf mode. in this case, the tag sends the frr response as soon as it is energized, even without the frr command. the tag has a short listening window (1 ms) immediately after the frr response. the inte rrogator sends its next command during this listening window. the frr response includes th e 32 bits of tag id and frf (blocks 3 -5). see tabl es 7-3, 7-4 and 7-6 for data. the interrogator identif ies which tags are in the field by receiving their frr responses. based upon the frr respon se, the interrogator will send matching code 1 (mc1 ) or matching code 2 (mc2) during the tag?s list ening window. the interroga- tor sends the mc1 to put the tag into sleep mode. tags in sleep mode never respond to any command. removal of the interrogator?s rf energy from the device is the only way to wake-up the device. if the tag needs further re ad/write processing, the interrogator sends the mc2, followed by a read or write command. after the completion of reading or writing of block data, the interrogator sends an end command to put the tag into sleep mode. the reading and writing of the frr devices takes place in the anti-collision mode. for instance, if there are multiple tags in the field, the interrogator selects one tag at a time by controlling the tag?s time slot for the frr response. the interrog ator repeats this sequence until all tags in its field are processed: - send frr command - receive frr response - send matching code 1 or 2 at tag?s listing window - send read block command/or send write block command and data - verify read/write response - send end command - verify the end command response - look for other tag?s frr responses 1.1.2 operation of tag in frb mode the communication with the device in the frb mode is initiated by the frb command only. if the device sees the interrogator?s frb command , it sends its 32-bit tag id and waits for the mc2. th is is followed by a read or write command. once the device is read or written, the interrogator sends an e nd command. unlike the frr mode, the reading and writi ng of the tag are processed in a non anti-collision mode. see section 6.0 ?read/write anti-collision logic? , for the read and write anti-collision algorithm. see example 9-1 for command sequences and device responses.
? 2003 microchip technology inc. ds40232h-page 5 MCRF450/451/452/455 2.0 electrical characteristics table 2-1: absolute ratings table 2-2: operating dc characteristics parameters symbol min max units conditions coil current into coil pad i pp _ ac ? 40 ma peak-to-peak coil current maximum power dissipation p mpd ?0.5w? ambient temperature with power applied t amb -40 +125 c ? assembly temperature t asm ? 300 c < 10 sec. storage temperature t store -65 150 c ? note: stresses above those listed under ?maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at those or any other conditions above those indicated in the operational listings of this specif ication is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. standard operating conditions (unless otherwise stated) operating temperature = -20c to +70c parameters symbol min typ max units conditions reading voltage v ddr 2.8 ? ? v v dd voltage for reading at 25c operating current in normal mode i oper _ n ?20? av dd = 2.8v during reading at 25c operating current in fast mode i oper _ f ?45? av dd = 2.8v during reading at 25c writing current i write ? 130 ? a at 25c, v dd = 2.8v writing voltage v write 2.8 ? ? v dc at 25 c modulation resistance r m ?3.05.0 ? dc turn-on resist ance between drain and source terminals of the modulation transistor at v dd = 2.8v data retention ? 200 ? ? years for t < 120c endurance ? 1.0 ? ? million cycles at 25c
MCRF450/451/452/455 ds40232h-page 6 ? 2003 microchip technology inc. table 2-3: operating ac characteristics standard operating conditions (unless otherwise stated) operating temperature = -20c to +70c. parameters symbol min typ max units conditions carrier frequency f c 2.0 13.56 35 mhz device data rate f m 58 70 82 khz manchester coding, both normal and fast modes, 70 khz 17% (note 1) pulse width of 1-of-16 ppm for normal mode pw ppm _ n 145 175 205 s see figure 6-2 and table 6-7, 175 s 17% pulse width of 1-of-16 ppm for fast mode pw ppm _ f 8.3 10 11.7 s see figure 6-2 and table 6-7 symbol duration of 1-of- 16 ppm for normal mode sw ppm _ n 2.32 2.8 3.28 ms see figure 6-9 symbol duration of 1-of-16 ppm for fast mode sw ppm _ f 133 160 187 s modulation index of gap pulse mod index _ gap 20 60 100 % see figure 6-2 gap width of interrogator command and data except fast mode data gap width _ n 20 100 150 s see figure 6-2 and table 6-7 gap width of fast mode data gap width _ f 6.0 7.0 8.0 s see figure 6-2 and table 6-7 coil voltage during reading v pp _ ac 4.0 ? ? v pp peak-to-peak voltage across the coil during reading detuning voltage v detune 3.0 4.0 ? v dc v dd voltage at which the input voltage limiting circuit becomes active eeprom (memory) writing time t write ? 5.0 ? ms write time for a 32-bit block command decode time t decode 0.97 1.225 1.48 ms time dela y between end of command symbol and start of the device response time slot t slot 2.1 2.5 2.93 ms listening window t lw 0.82 1.0 1.17 ms command duration of fast read command (frr and frb) t_cmd_ frr 1.305 1.575 1.845 ms 175 s/pulse position x 9 pulse positions = 1.575 ms internal resonant capacitor c res _100 85.5 95 104.5 pf between ant. a and v ss pads at 13.56 mhz and at 25c (mcrf451) see figure 2-3 c res _2_50 27 30 33 pf between ant. a and v ss pads at 13.56 mhz and at 25c (mcrf452) see figure 2-4 c res _50 45 50 55 pf between ant. a and v ss pads at 13.56 mhz and at 25c (mcrf455) see figure 2-5 parasitic input capacitance of MCRF450 c para _ in ? 3.5 ? pf between antenna pad a and v ss , at 13.56 mhz with modulation transistor off (no external coils). not tested in production note 1: tested in production at v dd = 2.8 v dc and 5.0 v dc .
? 2003 microchip technology inc. ds40232h-page 7 MCRF450/451/452/455 table 2-4: pad coordinates (microns) table 2-5: die mechanical dimensions table 2-6: wafer mechanical specifications pad name lower upper passivation openings pad center x pad center y left x left y right x right y pad width pad height ant. pad a -853.50 -992.10 -764.50 -903.10 89.00 89.00 -809.00 -947.60 ant. pad b 759.50 -993.70 848.50 -904.70 89.00 89.00 804.00 -949.20 v ss 769.10 977.90 858.10 1066.90 89.00 89.00 813.60 1022.40 v dd -839.50 45.50 -750.50 134.50 89.00 89.00 -795.00 90.00 clk 721.10 77.80 810.10 166.80 89.00 89.00 765.60 122.30 f clk -821.50 910.70 -732.50 999.70 89.00 89.00 -777.00 955.20 note 1: all coordinates are referenced from the center of the die. specifications min typ max unit comments bond pad opening ? ? 3.5 x 3.5 89 x 89 ? ? mil m note 1 , note 2 die backgrind thickness 7.5 190.5 8 203.2 8.5 215.9 mil m sawed 8? wafer on frame (option = wf) (note 3) 10 254 11 279.4 12 304.8 mil m bumped, sawed 8? wafer on frame (option = wfb) unsawed wafer (option = w) unsawed 8? bumped wafer (option = wb), (note 3) die passivation thickness (multilayer) ? 1.3 ? m note 4 die size: die size x*y before saw (step size) die size x*y after saw ? ? 1904 x 2340.8 1840.5 x 2277.3 ? ? m m ? ? note 1: the bond pad size is that of the passivation opening. the metal overlaps the bond pad passivation by at least 0.1 mil. 2: metal pad composition is 98.5% alum inum with 1% si and 0.5% cu. 3: as the die thickness decreases, susceptibility to crackin g increases. it is recomme nded that the die be as thick as the appl ication will allow. 4: the die passivation thickness (1.3 m) can vary by device dependi ng on the mask set used. the passivation is formed by: - layer 1: oxide (undoped oxide) - layer 2: psg (doped oxide) - layer 3: oxynitride (top layer) 5: the conversion rate is 25.4 m/mil. notice: extreme care is urged in the hand ling and assembly of die products since they are susceptible to mechanical and electrostatic damage. specifications min typ max unit comments wafer diameter ? 8 ? inch die separation line width ? 80 ? m dice per wafer ? 6,600 ? die batch size ? 24 ? wafer
MCRF450/451/452/455 ds40232h-page 8 ? 2003 microchip technology inc. figure 2-1: MCRF450/451/452/455 die layout f clk ant. a ant. b clk vss 1590.6 865.2 1037.6 1071.5 900.1 1613 x y top view die size before saw: bond pad size: (notch edge of wafer) 1.904 mm x 2.3408 mm 74.96 mil x 92.16 mil 0.089 mm x 0.089 mm 3.5 mil x 3.5 mil v dd die size after saw: 1.8405 mm x 2.2773 mm 72.46 mil x 89.66 mil bumped die: bump height: 25 m 3 m bump size: 103 m x 103 m (covered all passivation opening of bond pad) other area except the four bumped pads: covered by polyamide 1904.0 m x 2340.8 m 1840.5 m x 2277.3 m 89 m x 89 m bumped pad: four corner pads (f clk , v ss , antenna b, antenna a) bumping material: 99.6% gold thickness of polyamide: 3 m note: coordinate units are in m. see table 2-5 for die mechanical dimensions.
? 2003 microchip technology inc. ds40232h-page 9 MCRF450/451/452/455 table 2-7: pad function table figure 2-2: external circuit configuration for MCRF450 name function ant. pad a connected to antenna coil l1. ant. pad b connected to antenna coils l1 and l2 for MCRF450/451/455, nc for mcrf452. v ss connected to antenna coil l2. device ground during test mode. (v ss = substrate) f clk for device test only. leave floating or connect to v ss in applications. clk v dd for device test only. leave floating in applications. note: nc = not connected. ant. a ant. b l1 v ss l2 c MCRF450 note: substrate = v ss l1 > l2 (a) two inductors and one capacitor f tuned 1 2 l t c --------------------- - = f detuned 1 2 l 1 c --------------------- - = l t l 1 l 2 2 l m ++ = where: l m = mutual inductance of l1 and l2 l t = total antenna inductance between ant. a and v ss l m kl 1 l 2 = k = coupling coefficient of two inductors (0 k 1) ant. a ant. b l v ss c1 MCRF450 note: substrate = v ss c1 c2 (b) one inductor and two capacitors f tuned 1 2 l t c t ------------------------- - = f detuned 1 2 lc 1 --------------------- - = c t c 1 c 2 c 1 c 2 + -------------------- = c2 note: input parasitic capacitance between antenna a and v ss pads = 3.5 pf. see application notes, an710 and an830 for antenna circuit design.
MCRF450/451/452/455 ds40232h-page 10 ? 2003 microchip technology inc. figure 2-3: external circuit configuration for mcrf451 figure 2-4: external circuit configuration for mcrf452 figure 2-5: external circuit configuration for mcrf455 note: substrate = v ss internal resonant capacitor (cres_100) = 95 pf l1: external antenna coil a l2: external antenna coil b ant. a ant. b l1 v ss l2 mcrf451 int. res. cap. l1 > l2 f tuned 1 2 l t () 95 12 ? 10 ------------------------ ----------------------- - = f detuned 1 2 l 1 () 95 12 ? 10 ---------------------------- ------------------- = l t = total antenna inductance between ant. a and v ss = 95 pf ant. a ant. b l v ss mcrf452 internal resonant capacitor between ant. a and v ss pads: c res _2_50 + parasitic capacitor = 30 pf note: substrate = v ss f tuned 1 2 l () 30 12 ? 10 ------------------------------------------- = f detuned 1 2 l () 50.6 12 ? 10 ----------------------- ------------------------ - = int. res. cap. = 30 pf 50.6 pf 65.4 pf internal resonant capacitor (cres_50) = 50 pf l1: external antenna coil a l2: external antenna coil b ant. a ant. b l1 v ss l2 mcrf455 f tuned 1 2 l t () 50 12 ? 10 ------------------------ ----------------------- - = f detuned 1 2 l 1 () 50 12 ? 10 ------------------------- ---------------------- = l t = total antenna induct ance between ant. a and v ss note: substrate = v ss l1 > l2 int. res. cap. = 50 pf note: see application notes an 710 and an830 for antenna circuit design of figure 2-2 through figure 2-5.
? 2003 microchip technology inc. ds40232h-page 11 MCRF450/451/452/455 table 2-8: internal resonant ca pacitance and antenna inductance requirements device name resonant capacitance (antenna a to v ss ) external inductance requirement between antenna a and v ss for 13.56 mhz tag connection to external antenna circuit reference mcrf451 95 pf 10% 1.45 h 10% antenna a, b, and v ss pads this device requires three connections to an external circuit. good for direct die attachment onto antenna. mcrf452 30 pf 10% 4.591 h 10% antenna a and v ss pads this device requires only two antenna connections . good for both direct die attachment and cob. mcrf455 50 pf 10% 2.76 h 10% antenna a, b, and v ss pads this device requires three connections to an external circuit. good for direct die attachment onto antenna. note: the internal capacitance value for bumped die is abo ut 1 pf higher than the unbumped die?s capacitor.
MCRF450/451/452/455 ds40232h-page 12 ? 2003 microchip technology inc. 3.0 block diagram the device contains four major sections. they are: analog front-end, detect ion/encoding, read/write anti-collision logic and memo ry sections. figure 3-1 shows the block diagram of the device. figure 3-1: block diagram time slot generator clock generator to memory modulation memory section memory array high/low voltage power-on reset v dd read/write anti-collision section anti-collision command controller regulator demodulator (detector) ppm command crc/parity generator and checker data encoder time slot registers (high voltage) main clock from high voltage (hv) external antenna circuit to anti-collision command controller ( v dd ) v dd from por (por) high voltage regulator analog front-end section detection/encoding section fast mode counter detuning circuit v dd oscillator (tc, tsmax, tag id) decoder decoder
? 2003 microchip technology inc. ds40232h-page 13 MCRF450/451/452/455 figure 3-2: data waveform of device data nrz - l biphase - l (manchester) 1 signal waveform description digital data non return to zero - level ? 1 ? is represented by logic high level. ? 0 ? is represented by logic low level. biphase - level (split phase) a level change occurs at middle of every bit clock period. ? 1 ? is represented by a high to low level change at midclock. ? 0 ? is represented by a low to high level change at midclock. clk internal clock signal (reference only) 0110001101 0
MCRF450/451/452/455 ds40232h-page 14 ? 2003 microchip technology inc. 4.0 analog front-end this section includes high and low voltage regulators, power-on reset, 70 khz clock generator and modulation circuits. 4.1 high and low voltage regulator the high voltage circuit generates the programming voltage for the memory sectio n. the low voltage circuit generates dc voltage (v dd ) to operate the device. 4.2 power-on reset (por) this circuit generates a power-on reset (por) voltage. the por releases when sufficient power has been developed by the volt age regulator to allow for correct operation. 4.3 clock generator this circuit generates a clock (clk). the main clock is generated by an on-board 70 khz time base oscillator. this clock is used for all timing in the device, except for the fast mode ppm decoding. 4.4 data modulation the data modulation circuit consists of a modulation transistor and a lc reso nant circuit. the resonant circuit must be tuned to th e carrier frequency of the interrogator (i.e., 13.56 mhz) for maximum performance. the modulation transistor is placed between antenna b and v ss pads. it is designed to result in the turn-on resistance of less than five ohms (r m ). this small turn- on resistance shorts the re sonant circuit component between antenna b and v ss pads as it turns on. this results in a change of the resonant frequency of the resonant circuit. consequen tly, the resonant circuit becomes detuned with respec t to the carrier frequency of the interrogator. the vo ltage across the resonant circuit is minimized during this time. this condition is called ?cloaking?. the transistor, however, rele ases the resonant circuit as it turns off. therefore, the resonant circuit tunes to the carrier frequency of th e interrogator again and develops maximum voltage . this condition is called ?uncloaking?. the device transmits data by cloaking and uncloaking, based on the on/off condition of the modulation transis- tor. using the 70 khz manchester format, the data bit ? 0 ? will be sent by cloaking and uncloaking the device for 7 s each. similarly, the data bit ? 1 ? will be sent by uncloaking and cloakin g the device for 7 s each. see figure 6-1 for the manchester waveform. 4.5 detuning circuit the purpose of this circuit is to prevent excessive rf voltage across the resonant circuit. this circuit monitors v dd and detunes the resonant circuit if the rf coil voltage exceeds the threshold limit (v detune ), which is above the o perating voltage of the device.
? 2003 microchip technology inc. ds40232h-page 15 MCRF450/451/452/455 5.0 detection and encoding this section encodes data with the manchester format and also detects commands from the interrogator. 5.1 demodulator (detector) this circuit demodulates the interrogator commands and sends them to the ppm decoder. 5.2 fast mode oscillator this oscillator generates a clock frequency that is used for decoding fast mode commands. 5.3 ppm signal decoder this section decodes the ppm signals and sends the results to the command decoder and crc/parity checker. 5.4 command decoder this section decodes the interrogator commands and sends the results to the anti-collision/command controller. 5.5 crc/parity generator and checker this section generates cyclic redundancy code (crc) and parity bits for transmitting and receiving data. the device utilizes a 16-bit crc for error detection. its polynomial and initial values are: crc polynomial: x 16 +x 12 +x 5 +x 0 initial value: $ffff this polynomial is also known as crc ccitt (consultative committee for international telegraph and telephone). the interrog ator also uses the same crc for data processing. th e device uses the crc in the following ways: 1. crc for blocks (except blocks 0 and 2): the interrogator will send a write command with crc. when the device receives this command, it checks the crc prior to any processing. if it is a correct crc, the device programs the block data and also stores th e crc in the eeprom. as soon as the data is written into memory, both the programmed data and stored crc (scrc) are sent back to the inte rrogator as verification. the device also send s the programmed data and scrc when there is a response to the read command. if the crc is incorrect, the device ignores the incoming message (does not respond to the interrogator) and wait s for the next command with a correct crc. 2. crc for blocks 0 and 2: when reading block 0 or 2, a calculated crc (ccrc) is sent. this is because both the tf an d fr bits in block 0 are non write-protectable, while the rest of the bits in the block are write-protectable. this means the scrc in the block no longer repre- sents the crc of the block data, if only the tf or the fr bit is reprogrammed. this is also true for block 2, which is a write protection block. the write-protected bit cannot be reprogrammed once it has been writte n. therefore, the scrc in blocks 0 and 2 are not used. instead, the device calculates the current crc of the block and sends it to the interrogator. 3. crc for frr response: for the fast read (fr) response (this is the device response to an frr command), the ccrc of the tag id and frf (blocks 3-5) data is sen t. the data length of the frf is determined by df bits (see table 7-6). 5.6 data encoder this section multiplexes seri al data, encodes it into manchester format and se nds it to the modulation circuit. see figure 3-2 for the manchester waveform.
MCRF450/451/452/455 ds40232h-page 16 ? 2003 microchip technology inc. 6.0 read/write anti-collision logic this section includes the anti- collision algorithm of the device and consists of the anti-collision/command controller, the time slot gen erator and the time slot counter. 6.1 description of algorithm the read/write anti-collision algorithm is based on time division multiplexing of ta g responses. each device is allowed to communicate with the interrogator in its time slot only. when not in its assigned time slot, the device remains in a nonmodulating condition. this enables the interrogator to communicate with other devices in the same interrogator field wi th fewer chances of data collision. figure 6-1 shows the anti-col lision algorithm flowchart, which consists of four control loops. they are: detection, processing, sl eeping and reactivation loops. all devices in the interrogator?s rf field are controlled by five differ ent commands and internal control flags. the interrogator commands are: 1. fast read request (frr): if the tf bit (bit 30 or block 0) is cleared, the device re sponds only to the frr command. the frr command consists of five specially timed gap pulses (refer to figures 6-3 to 6-7). the position of the five gap pulses in the given time span (1.575 ms) determines the parameters of the command. the command has three parameters: tcmax, tsmax and data transmission speed. the details of these paramete rs will be discussed in the following sections. if the device receives the frr command, it sends the fr response and then listens for 1 ms (t lw ) for a matching code from the interrogator. 2. fast read bypass (frb): this command is used in the reactivation loop and is only appli- cable to a device with the fr bit (bit 31 in block 0) cleared. the device responds with 64 bits of data, which includes block 1 data (32-bit tag id), and then listens for 1 ms (t lw ) for a match- ing code from the interrogator. the command structure is the same as the frr command: five specially timed gap pulses (1.575 ms). the command parameter (figure 6-8) determines the data rate (normal speed or fast speed) of subsequent interrogator commands. 3. matching code 1 (mc1): this command consists of time ca libration pulses (tcp) followed by 1-of-16 ppm signals. it is used when the device does not need any further process- ing. this mc1 command causes a device, which is in the detection loop, to enter the sleeping loop. 4. matching code 2 (mc2) : the command structure is the same as mc1: tcp followed by 1-of-16 ppm signals. the command is used when the device needs further processing (read/ write). the device enters the processing loop if it receives this command in the detection loop. the mc1 and mc2 matching code command consists of 12 bits or 3 symbols. the first 8 bits, or the first two symbols, are selected from the 32-bit tag id. the next 4 bits, or the 3rd symbol, determine the matching code type (3 bits) and a parity bit (see section 6.2.3.6 ?calculation of matching code? ). the command lasts for about 11.2 ms, including the tcp. 5. end process (ep): this command consists of the time reference pulses followed by 1-of-16 ppm signals. the ep command causes a device to exit the processing loop and enter the sleeping loop. 6.1.1 detection loop if the fr bit (bit 31 of bl ock 0) is set, the device can enter this loop in two ways , depending on the condition of the tf bit (bit 30 of block 0). they are: 1. when the tf bit is clea red, the device enters this loop and waits for a frr command. this is called the ?interrogator-t alks-first? (itf) mode. 2. when the tf bit is set, the device enters this loop by transmitting the fr response without waiting for an frr command. this is called the ?tag-talks-first? (ttf) mode. for case 1 above, the pa rameters of the frr are: maximum number of time slots (tsmax = 1, 16, or 64), maximum transmission counter (tcmax = 1, 2, or 4), data transmission speed (normal or fast mode). the purpose of the tsmax and tcmax parameters is to acknowledge the device in the detection loop as fast as possible. tsmax repres ents the maximum number of time slots between the end of the frr command and the beginning of the fr response. one time slot (t slot ) represents 2.5 ms. for example, tsmax = 64 represents a maximum time delay of 160 ms before sending the fr response. see section 6.3 ?time slot generator? for the calculation of actual time delay. tcmax represents the maximum number of fr responses a device can s end after an frr command. for example, tcmax = 4 means the device can send its fr response four times (after the frr command) for acknowledgment (matching code).
? 2003 microchip technology inc. ds40232h-page 17 MCRF450/451/452/455 the tsmax and tcmax values are determined by the interrogator?s decision on how many tags are in the field. the interrogator may assign tsmax = 1 and tcmax = 1, assuming there is only one tag in the field. the efficiency of the detection will increase in multiple tag environments by assigning a higher number to both the tsmax and tcmax. if the device receives the frr, it clears the position 1 flag, waits for its time slot, replies with the fr respon se and then listens for 1 ms. the fr response consists of a maximum of 160 manchester data bits (defau lt: 96 bits), which includes the 32-bit tag id and the frf data (blocks 3-5) (see table 6-3 and example 9-1). to acknowledge the fr response, the interrogator can start to send a matching co de (mc) during the device?s 1 ms listening window (t lw ). the mc is encoded with 1-of-16 ppm signal (see figure 6-9). the mc1 is given to the device if the device does not need any further processing. if the device rece ives the mc1, it enters the sleeping loop and stays in th e loop in a nonmodulating condition. the mc2 command is given to the device if further processing (read/write) is required. if the device receives the mc2 command, it enters the processing loop. if the device misses the mc within the listening window, it sends the fr response a gain after its time slot when two conditions are met: (1 ) position 1 flag is cleared and, (2) tcmax has not elapsed. the device checks the condition (elapsed or not elapsed) of tcmax using an internal transmission counter (tc). the tc consists of 3 bits. if the position 1 flag is cleared, the device increments the tc by 1 each time it does not receive a mc during its listening window. see figure 6-1 for a flow chart showing the condi tional incrementing of the transmission counter. table 6-1 shows an example of detecting the elapsed tcma x using a rolling modulo-8 transmission counter. for the ttf case, the device repeats its fr response (as long as it is energized) according to the tcmax and tsmax parameters, as specified in table 7-5. even though the device is op erating in the ttf mode, it will respond to its corr ect mc during its listening window. if tcmax = 1, 2 or 4, it will also respond to frr commands, just as in the itf case (see section 6.1.1.1 ?matching code queuing? ). 6.1.1.1 matching code queuing once the device receives the frr command, it sends the fr response and waits for a matching code (mc) during its listening window. if the device does not receive its correct mc code before its tcmax has elapsed (see table 6-1), it goes back to the beginning of the detection loop (posit ion 1 in the loop) and waits for either a new frr command or for the mc1 or mc2 matching code. this is ca lled ?matching code queuing?. in this queuing, the device stays in the detection loop waiting for an interrogator command (frr or mc). this queuing takes place within the detection loop and is controlled by the condition s of "set position 1 flag" and tcmax. this queuing allows the in terrogator to communicate with a device outside its li stening window. the result is enhanced and accelerated processing of individual devices in a multiple tag environment. table 6-1: conditions for tcmax = elapsed for itf mode 6.1.2 processing loop the reading and writing proc esses take place in this loop. devices in this loop are waiting for commands for processing. in order to read from, or write to, the device, its ?processing flag? (pf) must be set. any device entering this loop with its pf cleared is called a ?follow-along? tag. this foll ow-along tag in the loop is not processed for reading or writing. if the device with the pf flag set receives the ep command, it exits this lo op and enters the sleeping loop. however, the same ep command sends the follow-along tag back to the detection loop. if the device receives the frr or frb command in this loop, it sees the command as invalid, resets itself and goes back to the initial power-up state. 6.1.3 sleeping loop the sleeping loop is used to keep all processed devices in a ?silent? conditi on. the devices stay in this loop in a nonmodulating co ndition as long as they remain in the field. rolling modulo -8 tc tcmax = 1 tcmax = 2 tcmax = 4 001 elapsed ? ? 010 elapsed elapsed ? 011 elapsed ? ? 100 elapsed elapsed elapsed 101 elapsed ? ? 110 elapsed elapsed ? 111 elapsed ? elapsed 000 elapsed elapsed ?
MCRF450/451/452/455 ds40232h-page 18 ? 2003 microchip technology inc. 6.1.4 reactivation loop the reactivation loop is us ed to process a device with its fr bit cleared. a device in this loop waits for the frb command. if a device receives the frb command, it transmits the contents of block 1 (tag id) to its memory and waits for a mc2 in its listening window. if the device receives the mc2, it leaves this loop and enters the processing loop. this reactivation loop has no anti-collision capability. it is designed for reactivation of single devices. this loop can be effectively used in retail store applications to process returning items from customers.
? 2003 microchip technology inc. ds40232h-page 19 MCRF450/451/452/455 figure 6-1: anti-collision flow chart fr bit set ? no no yes no no no listen for frb command decode frr command frb received? send frr response send frb response wait 1, 16, or 64 time slot no yes yes no no yes yes execute command wait for commands decode command at correct speed valid command? read or write command? end command? maintain logic state reactivation processing sleeping talk-first bit set? yes yes yes yes power-up tc > 0? frr 1 tcmax elapsed ? ppm symbol? clear position 1 flag listening window expired? receiving? 3 ppm symbols? 3rd symbol =mc1? correct matching code? 3rd symbol =mc2? set position 1 flag clear processing flag position 1 flag set? increment transmission counter (tc) no yes no no no yes no no yes yes correct matching code? yes no yes no yes yes no yes no window expired? set processing flag processing flag set? yes processing flag set? yes no yes no ye s receiving? listening 3 ppm symbols? 3rd symbol =mc2? correct matching code? no ye s no ye s no ye s no no in tuned state tc=0 set processing flag command? (tag id: block 1 data) (tag id + frf data) (do not listen to any command) detection
MCRF450/451/452/455 ds40232h-page 20 ? 2003 microchip technology inc. 6.2 anti-collision command controller this section discusses the anti-collision algorithm and describes the communi cations between the interrogator and device. 6.2.1 structure of read/ write command signals the interrogator?s re ad/write commands have the following structure: read/write command = command + address + data + parity (or crc) the commands are summarized in the table below: table 6-2: read/write commands from interrogator to device note: command and address are sent msn (most significant nibble) first. data and parity/crc are sent lsn (least significant nibble) first. calculation of parity and crc includes command code, address, and data. see microchip appl ication note an752 (ds00752) for the crc-16 calculation algorithm. interrogator command command code address data parity or crc symbol length unused 0xx xxxxx ? ? ? read 32-bit block 110 aaaaa ? parity 3 symbols unused 111 00xxx ? ? ? unused 111 0100x ? ? ? end process 111 01010 ? parity 3 symbols unused 111 01011 ? ? ? unused 111 011xx ? ? ? unused 111 1000x ? ? ? set talk first bit 111 10010 ? parity 3 symbols set fr bit 111 10011 ? parity 3 symbols clear talk first bit 111 10100 ? parity 3 symbols clear fr bit 111 10101 ? parity 3 symbols unused 111 1011x ? ? ? unused 111 11xxx ? ? ? unused 100 xxxxx ? ? ? write 32-bit block 101 aaaaa 32 bits crc-16 14 symbols legend: aaaaa = block address x = don?t care
? 2003 microchip technology inc. ds40232h-page 21 MCRF450/451/452/455 6.2.2 structure of device response when the device receives the interrogator command, it responds with 70 khz manchester encoded data having the following structures: device response to frr command: preamble (8 bits) + tc (3 bits) + tp (4 bits) + ? 0 ? + 32 bits of tag id (block 1 data) + frf data (32 - 96 bits) + calculated crc (scrc, 16 bits) of tag id and frf data = 96 - 160 bits depending on frf data length. note: the preamble + tc + tp + ? 0 ? are not included for the crc calculation. device response to frb command: preamble (8 bits) + ? 00001 ? + ? 000 ? + 32 bits of tag id (block 1 data) + stored crc (scrc, 16 bits) of block 1 = 64 bits. device response of interrogator?s read command for blocks 0 and 2: preamble (8 bits) + block number (5 bits) + ? 000 ? + block data (32 bits) + calculated 16 bit crc (ccrc). note: the ccrc is calculated by using block number and block data only. preamble and ? 000 ? are not included in the crc calculation. device response of interrogator?s read command for all other blocks: device response = preamble (8 bits) + block number (5 bits) + ? 000 ? + block data (32 bits) + stored crc (scrc, 16 bits) in the same block. table 6-3: interrogator commands and device responses interrogator command delay device response read block 0 and block 2 data t decode preamble, block #, ? 000 ?, block data, ccrc read block data except for block 0 and block 2 t decode preamble, block #, ? 000 ?, block data, scrc write block data t write for blocks 0 and 2: pr eamble, block #, ? 000 ?, block data, ccrc for all others: preamble, block #, ? 000 ?, block data, scrc set fast read (fr) bit t write preamble, 1 byte ? 0 ?s, block 0 data, ccrc clear fast read (fr) bit t write preamble, 1 byte ? 0 ?s, block 0 data, ccrc set talk first (tf) bit t write preamble, 1 byte ? 0 ?s, block 0 data, ccrc clear talk first (tf) bit t write preamble, 1 byte ? 0 ?s, block 0 data, ccrc end process (ep) t decode preamble frr f(tsmax, tcmax, 8-bit t ag id) preamble,tc, tp, ? 0 ?, tag id, frf, frr_ccrc frb t decode preamble, address of block #1 (? 00001 ?), ? 000 ?, tag id (32 bits), scrc of block 1 references used in this table are as follows: preamble = 11111110 (8 bits).? 0 ? is transmitted last. block # = 5 bit addressed block, tr ansmits least significant bit (lsb) first. block data = 32-bit data of the ad dressed block, transmits lsb first. ccrc = calculated crc of the preceding blo ck number and block data. transmits lsb first. scrc = stored crc. this scrc is the crc of the write command, address, and data from the interrogator, lsb first. the device stores the received crc for each block. see section 7.2 ?stored crc (scrc) memory section? for details. frr_crc = calculated crc of 32-bit t ag id and fast read field (frf) data. tp = tag parameters (4 bits: ? 0 ?, df0, df1, parity). where df0 and df1 determine the fr field length (see table 7-6). tc = transmission counter (3 bits), transmits lsb first. parity = even parity bit of tc and tp. tag id = 32 bits of unique ident ification code of the device, transmits lsb firs t. this tag id is preprogrammed in the factory prior to shipping. 8-bit tag id = 8 bits of tag id selected from the 32 bits of the unique tag identification code. transmits lsb first (see section 6.2.3.6 ?calculation of matching code? for selecting the 8 bits from the tag id). frf = fast read field (blocks 3- 5), transmits lsb first (see section 7.0 ?memory section? ). f(tsmax, tcmax, 8-bit tag id = delay is a function of the tsmax, tcmax and 8-bit tag id. t write = writing time for eeprom (see table 2-3). t decode = time requirement for command decoding (see table 2-3). examples are given in section 9.0 ?examples? .
MCRF450/451/452/455 ds40232h-page 22 ? 2003 microchip technology inc. 6.2.3 detection of interrogator commands the interrogator sends co mmands to the device by amplitude modulating the carrier signal (gap pulse). the interrogator uses two classes of encoding signals for modulation. they are (1) 1-of-16 ppm for data transmission, and (2) sp ecially timed gap pulse sequence for the frr a nd frb commands. these commands consist of five gap pulses within nine possi- ble gap pulse positions (1.5 75 ms). the combination of the possible gap positions determines the command type and parameters of the fast read command. the interrogator also sends tcp prior to the 1-of- 16 ppm. the tcp is used to calibrate the time-base of the decoder in t he device. the specifics of the two encoding methods and the tc p are described in the following sections. 6.2.3.1 fast read (fr) commands the fr commands are co mposed of five 175 s wide gap pulses (see figure 6-2) whose spacing within 1.575 ms determines the command type and its param- eters. table 6-4 shows the specification of the gap signal for the fr commands . two commands are used for the fast read. they ar e: (1) fast read request (frr) in the detection loop, and (2) fast read bypass (frb) in the reactivation loop. see tables 6-5 and 6-6 for the frr gap pulse positi ons. see figures 6-3 to 6-8 for the gap modulation patterns. the parameters of frr are: (1) number of time slots (tsmax = 1,16, or 64), (2) maximum transmission counter (tcmax) and (3) data transmission speed. the frb has only a data tr ansmission speed parame- ter (normal or fast speed mode). the device extracts these parameters based on the positions of the five gap pulses within the 1.575 ms time span, as shown in figures 6-3 to 6-8. tsmax = 1 is given if there is only one device in the field. this is called ?conv eyor mode? or ?single tag environment?. in this mode , the device responds with the fr response signal in every time slot until it receives a correct matchi ng code, or until tcmax is elapsed. 6.2.3.2 data transmission speed the interrogator can send data with two different data rates: (1) normal and (2 ) fast speed modes. the normal speed uses 2.8 ms/symbol, while the fast speed uses 160 s/symbol. one symbol represents one 4-bit data packet (see section 6.2.3.4 ?1-of-16 ppm? ). the data transmissi on speed is a parameter of the frr and frb commands. this parameter indicates the data speed of subsequent interrogator commands. the data rate of the device output (70 khz) is not affected by this parameter. table 6-4: specification of gap signal for frr and frb commands number of gaps for one command 5 total available number of gap positio ns within the command time span 9 command time span 1.575 ms gap pulse width 175 s
? 2003 microchip technology inc. ds40232h-page 23 MCRF450/451/452/455 table 6-5: specification of modulation sequence for frr command table 6-6: specification of modulation sequence for frb command maximum time slot (tsmax) tcmax gap pulse position data transmission mode 1 1 1, 2, 3, 4, 6 normal speed 1, 3, 5, 6, 8 fast speed 2 1, 2, 3, 4, 5 normal speed 1, 3, 5, 6, 7 fast speed 4 1, 2, 3, 5, 6 normal speed 1, 3, 5, 7, 8 fast speed 16 1 1, 2, 4, 6, 8 normal speed 1, 3, 4, 6, 8 fast speed 2 1, 2, 4, 6, 7 normal speed 1, 3, 4, 6, 7 fast speed 4 1, 2, 4, 5, 6 normal speed 1, 3, 4, 5, 6 fast speed 64 1 1, 2, 4, 5, 7 normal speed 1, 3, 4, 5, 7 fast speed symbol gap pulse position data transmission mode frb_n 1, 2, 3, 5, 7 normal speed frb_f 1, 3, 5, 7, 9 fast speed
MCRF450/451/452/455 ds40232h-page 24 ? 2003 microchip technology inc. figure 6-2: pulse waveform of gap and 1-of-16 ppm signals table 6-7: waveform characteristics of gap and 1-0f-16 ppm signals signal symbol min typ max unit conditions gap signal and 1-of-16 ppm for normal mode t1 145 175 205 spw ppm _ n t2 20 100 150 s measured at 50%, see figure 6-2 gap width _ n mod index _ gap 20 60 100 % see figure 6-2 1-of-16 ppm for fast mode t1 8.3 10 11.7 spw ppm _ f t2 6.0 7.0 8.0 s measured at 50%, see figure 6-2 gap width _ f mod index _ gap 20 60 100 % see figure 6-2 100% 50% t2 t1 0% a b a b a b (a) example of interrogator?s signal received at tag?s antenna coil. see table 6-7 for the specifications of t1, t2, and modulation d epth (modulation index). the modulation index is defined as: modulation index ab ? ab + ------------- 100% = (b) frr command waveform for figure 6-3 (a) with near 100% modulation index (c) frr command waveform for figure 6-3 (a) with near 20% modulation index
? 2003 microchip technology inc. ds40232h-page 25 MCRF450/451/452/455 the following figures show the various modulation patterns of the fast read commands (frr and frb). each command consists of a combination of five gap pulses within nine possible gap positions. the pulse width of each gap is 175 s and the total time span of each command for the ni ne possible positions is 1.575 ms (175 s x 9 = 1.575 ms). in the figures, p mn represents m th gap pulse at n th gap position in the given data packet (symbol). figure 6-3: gap modulation patterns for frr, normal speed, tsmax = 1 figure 6-4: gap modulation patterns for frr, fast speed, tsmax = 1 (a) tcmax = 1 (b) tcmax = 2 (c) tcmax = 4 1600 200 400 600 800 1000 1200 1400 p11 p22 p33 p44 p56 200 400 600 800 1000 1200 1400 1600 200 400 600 800 1000 1200 1400 1 0.5 0 1 0.5 0 1 0.5 0 p11 p22 p33 p44 p55 p11 p22 p33 p45 p56 1400 ( s) ( s) 1600 ( s) (a) tcmax = 1 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p35 p46 1 0.5 0 1400 p58 (b) tcmax = 2 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p35 p46 1 0.5 0 1400 p57 (c) tcmax = 4 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p35 p47 1 0.5 0 1400 p58
MCRF450/451/452/455 ds40232h-page 26 ? 2003 microchip technology inc. figure 6-5: gap modulation patterns for frr, normal speed, tsmax = 16 figure 6-6: gap modulation patterns for frr, fast speed, tsmax = 16 figure 6-7: gap modulation patterns for frr, tsmax = 64, tcmax = 1 (a) tcmax = 1 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p22 p34 p46 p58 1 0.5 0 1400 (b) tcmax = 2 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p22 p34 p46 p57 1 0.5 0 1400 (c) tcmax = 4 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p22 p34 p45 p56 1 0.5 0 1400 (a) tcmax = 1 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p34 p46 1 0.5 0 1400 p58 (b) tcmax = 2 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p34 p46 1 0.5 0 1400 p57 (c) tcmax = 4 ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p34 p45 1 0.5 0 1400 p56 (a) normal speed ( s) 1600 200 400 600 800 1000 1200 1400 p11 p22 p34 p45 p57 1 0.5 0 1400 (b) fast speed ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p34 p45 p57 1 0.5 0 1400
? 2003 microchip technology inc. ds40232h-page 27 MCRF450/451/452/455 figure 6-8: gap modulation patterns for frb (fast request bypass) (a) normal speed ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p33 p45 p57 1 0.5 0 1400 (b) fast speed ( s) 1600 200 400 600 800 1000 1200 1400 p11 p23 p35 p47 1 0.5 0 1400 p59
MCRF450/451/452/455 ds40232h-page 28 ? 2003 microchip technology inc. 6.2.3.3 usage of tsmax and tcmax the parameters of tsmax and tcmax are determined by an expected number of tags in the detection loop. the follo wing table shows the recommended frr command repeat times for each of the 7 possible combinations of tsmax and tcmax. the command repeat time in table 6-8 is calculated by: equation 6-1: command repeat time table 6-8: frr command repeat time vs. (tsmax, tcmax) 6.2.3.4 1-of-16 ppm the interrogator uses 1-of-16 pulse position modulation (ppm) for mc1 and mc2 matching codes, end process (ep) and also commands in table 6-2. 1-of-16 ppm uses only one gap pulse in one of sixteen possible pulse positions for sending 4-bit symbols (2 4 = 16). this means one symbol (one data packet) represents 4 bits of binary data. one symbol lasts for 2.8 ms and 160 s for normal speed and fast speed mode, respectively. all communica- tions begin with time calibration pulses (tcp) composed of three pulses in positions, zero, six and fourteen of a 1-of-16 ppm symbol, as shown in figure 6-10. table 6-9: 1-of-16 ppm pulse specifications (tsmax, tcmax) (1,1) (1,2) (1,4) (16,1) (16,2) (16,4) (64,1) command repeat time 2.925 ms 5.85 ms 11.7 ms 46.8 ms 93.6 ms 187.2 ms 187.2 ms command repeat time tsmax tcmax 2.5 ms 1.17 = where: 1.17 is related to the to lerance of the baud rate. normal mode fast mode modulation depth (mod index _ gap ) 100% (max) 100% (max) pulse width 175 s (typical) 10 s (typical) gap width 100 s (typical) 7 s (typical) pulse positions per symbol 16 16 symbol width 2.8 ms (typical) 160 s (typical) calibration sequence pulses in positions 0, 6, 14 pulses in positions 0, 6, 14
? 2003 microchip technology inc. ds40232h-page 29 MCRF450/451/452/455 figure 6-9: 1-of-16 ppm representation for hex values for normal speed mode 0 ( s ) pw ppm _ n 175 350 525 700 875 1050 1225 1400 1575 1750 1925 2100 2275 2450 2675 ?0? ?1? ?2? ?3? ?4? ?5? ?6? ?7? ?8? ?9? ?b? ?c? ?d? ?e? ?f? ?a? gap position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 hex value 2800 order
MCRF450/451/452/455 ds40232h-page 30 ? 2003 microchip technology inc. 6.2.3.5 calibration of time reference for decoding the device uses tcp to match its internal decoder timing to the interrogato r timing. the interrogator transmits the timing pulses at the start of all commands and at least every 17 symbols. the tcp uses a code violation of the 1-of-16 ppm signal consisting of three gap pulse s within one symbol. the first gap pulse is located at position 0, the second gap pulse at position 6 and the third at position 14 of the symbol. the time period between the last two gap pulses is used to calibrate the device?s timing for decoding. figure 6-10 shows the calibration pulses for normal speed mode. the waveform of the gap pulses is the same as the 1-of-16 ppm signal, as shown in figure 6-2. for fast speed mode, the gap positions are the same. pw ppm _ f is the gap pulse width and sw ppm _ f is the symbol width of the fast mode. figure 6-10: calibration pulses for normak speed mode 6.2.3.6 calculation of matching code when the interrogator re ceives the fr response from a device, it sends an mc to select the device. the mc is sent during the device?s listening window. there are two different types of matching codes: mc1 and mc2. both mc1 and mc2 are used in the detection loop. mc2 is used in the reactivation loop, as detailed in figure 6-1. the mc1 command is used to send the device to the sleeping loop, while mc2 is used to send the device to the processing loop. the mc is an 8-bit ?match? of tag id followed by 4-bit matching code type and parity bit such that: matching code (12 bits) = ?match (8 bits of tag id)? + matching code type (3 bits)+ parity (1-bit) the matching code type and parity bit is bit-wise structured as follows: mc1: 010 p mc2: 100 p where p represents the parity bit of all match bits (8 bits) plus the mc type (3 bits). the ?match? part of the mc is 8 bits of the 32-bit tag id. the interrogator selects the 8 bits from the 32-bit tag id by calculating the bit range of the tag id. equation 6-2 shows the equation for selecting the bit range using the transmission counter (tc). both the 1 0.5 0 1000 2000 2500 3000 (ms) gap pulse width calibration time reference position 0 position 6 position 14 500 1500 500 (pw ppm _ n ) symbol width (sw ppm _ n )
? 2003 microchip technology inc. ds40232h-page 31 MCRF450/451/452/455 32-bit tag id and tc are in cluded in the fr response. an example for the calculation of the matching code is given in example 9-2. equation 6-2: bit-wise equation for ?match? 6.3 time slot generator this block generates time slots for the device. the time slot represents the time delay between the end of the frr command and the beginni ng of the fr response. the available time slots are 1, 16 or 64. one time slot represents 2.5 ms. the device calculates the actual time slot based on the tsmax, tc and tag id. the maximum time slot (tsmax) is assigned to the device by the frr command (see figures 6-3 to 6-7), or set to 16, if the tf bit is set. four or six bits out of the 32-bit tag id are used to calculate the time slot, with tc being the shift parameter to choose which po rtion of the 32-bit tag id is used, as shown in equation 6-3. equation 6-3: time slot calculation table 6-10: example: tag id = h825fe1a0 table 6-10 shows the calculated time slot (ts): 5 for tc = 1 and tsmax = 16 with tag id = h 825fe1a0 . this means the device waits for 12.5 ms (5 x 2.5 ms = 12.5 ms) in a nonmodulating condition between the end of frr and the start of the fr response. also, the ts is 37 for tc = 1 and tsmax = 64. this means the device waits fo r 92.5 ms (37 x 2.5 ms = 92.5 ms) between the end of frr and the start of the fr response in a nonmodulating condition. 6.4 time slot counter this section generates the sleep time (2.5 ms x ts) of the device. during the sleep time, the device remains in a nonmodulating condition. ?match? = tag id bit range a: b {4*tc} modulo 32: {4 (tc +1) + 3} modulo 32 where {} modulo 32 means the remainder of {} divided by 32. for exampl e, {28} modulo 32 and {35} modulo 32 are 28 and 3, respectively. tsmax time slot = tag id bit range a:b 64 {[4(tc+1)+1] modulo 32: [4 tc] modulo 32} xor tc lsb 16 {[4(tc+1)-1] modulo 32: [4 tc] modulo 32} xor tc lsb 10 note: the exclusive-or (xor) operation in equation 6-3 is called ?semi-inverting? in that it randomizes worst case tag ids; for example: a tag id of ? 77777777 ? or ? 00000000 ?. table 6-10 shows examples of the calculation. tc relevant tag id selected tag id before xor with lsb of tc calculated time slot (ts) (after xor with lsb of tc) hexadecimal binary tsmax = 16 tsmax = 64 tsmax = 16 tsmax = 64 0 h825fe1(a0) b?1010 0000? h0 h20 h0 d0 h20 d32 1 h825fe(1a)0 b?0001 1010? ha h1a h5 d5 h25 d37 2 h825f(e1)a0 b?1110 0001? h1 h21 h1 d1 h21 d33 3 h825(fe)1a0 b?1111 1110? he h3e h1 d1 h01 d1 4 h82(5f)e1a0 b?0101 1111? hf h1f hf d15 h1f d31 5 h8(25)fe1a0 b?0010 0101? h5 h25 ha d10 h1a d26 6 h(82)5fe1a0 b?1000 0010? h2 h02 h2 d2 h02 d2 7 h(08)25fe1a b?0000 1000? h8 h08 h7 d7 h37 d55 legend: h x..x represents hexadecimal number d x..x represents decimal number b x..x represents binary number
MCRF450/451/452/455 ds40232h-page 32 ? 2003 microchip technology inc. 7.0 memory section the memory section is organized into two groups: main memory section and stored crc (scrc) memory section. 7.1 main memory section the main section is organized into 32 blocks, as shown in table 7-1, with each block having 32 bits. each individual block can be read and written by the interro- gator?s command. the first bl ocks (0-2) are used for predefined parameters and device operation. the next three blocks (3-5) are used as the frf data. the blocks from 3 to 31 (2 9 blocks) are used for user data memory. bits from 0 to 15 of block 0 also can be used for user memory. the memory is read or written in 32-bit selectable units. th e exceptions are the fr bit and the tf bit of block 0, which are individually selectable. each block is accessed by the interrogator?s command based on block address. th e reading of frf blocks (blocks 3-5) can be accomplished in two different ways: (1) by frr command or (2) by read block command. the device sends the frf data when it receives the frr command. the length of the frf data for the frr command is determined by df bits (see table 7-6). 7.2 stored crc (scrc) memory section this memory section is used to store the crc of the main memory section. it is organized into 32 blocks. each block has 16 bits and contains the crc of the corresponding memory block. the stored crc (scrc) is the crc of the interroga- tor?s writing command (write command + block address + data). the devi ce stores the received interrogator?s crc and sends back verification when it sends the block data. for t he block 0 and 2, the device sends ccrc instead of the scrc. the device sends the crc of each block as follows: blocks 0 and 2: ccrc of block number and block data. other blocks except block 0 and 2: scrc. crc for frr response: ccrc of tag id and frf (blocks 3-5) data. the data length of the frf is determined by df bits (b0: 26-27). table 7-1: memory organization main memory section (32 blocks x 32 bits) stored crc section (32 blocks x 16 bits) comments m s b l s b 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 f r t f t f t d f m t t m available to user (21 bits) block 0 (tag parameters + user memory) byte 3byte 2byte 1byte 0 blo ck 1 (tag id = serial number) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 block 2 (write protection bits) (clear bit 2 to write-protect block 2) fast read field (ls block) block 3 (fr field least significant block) fast read field block 4 (fr field) fast read field (ms block) blo ck 5 (fr field most significant block) block 6 (user data) block 7 (user data) . . . . . . . . . . . . . . . . . . block 31 (user data)
? 2003 microchip technology inc. ds40232h-page 33 MCRF450/451/452/455 7.3 bit layout 7.3.1 block 0 the bit layout in block 0 is given in the following table. fr and tf bits are not write-protectable. table 7-2: bit layout of block 0 7.3.1.1 description of bits table 7-3: fr bit (b0:31) table 7-4: tf bit (b0:30) table 7-5: tft bits (b0:29 - b0:28) table 7-6: df bits (b0:27 - b0:26) b0:31 b0:30 b0:29 b0:28 b0:27 b0:26 b0:25 b0:24 fr tf tft1 tft0 df1 df0 mt1* mt0* b0:23 b0:22 b0:21 b0:20 b0:19 b0:18 b0:17 b0:16 tm2* tm1* tm0* user memory b0:15 b0:14 b0:13 b0:12 b0:11 b0:10 b0:9 b0:8 user memory b0:7 b0:6 b0:5 b0:4 b0:3 b0:2 b0:1 b0:0 user memory note: * these are ?hardwired? bits, not eeprom bits. fr reply to frr (fast read request) command reply to frb (fast read bypass) command application example 0 no yes (see example 9-1 for response) ?item? has been purchased in retail eas applications. 1 yes (see example 9-1 for response) no ?item? is unpaid in retail eas applications. note: fr bit is not write-protectable. tf condition 0 interrogator-talks-first (itf) mode: wa it for frr command for frr response. 1 tag-talks-first (tft) mode if fr bit is also set: send fast read response without waiting for frr command. note: tf bit is not write-protectable. tft1 tft0 tcmax 1 for tag-talks-first mode 00 1 01 2 10 4 11 never elapses (default) 2 note 1: only applicable in ttf mode. tsmax parameter is set to 64 for ttf mode. for the itf mode, the tcmax is given in the frr command. 2: the device continuously sends its fr response until it receives its correct matching code. on average, the device will send its fr response every 80 ms. df1 df0 fr data field length 00 32 bits (default) 01 48 bits 10 64 bits 11 96 bits
MCRF450/451/452/455 ds40232h-page 34 ? 2003 microchip technology inc. table 7-7: mt bits (b0:25 - b0:24) table 7-8: tm bits (b0:23 - b0:21) table 7-9: b0: (20-0) 7.3.2 block 1: unique 32-bit tag id block 1 contains 32 bits of unique tag id with scrc. the id is uniquely serialized by microchip technology inc. 7.3.3 block 2: write-protect for the first kbits each bit corresponds to a 32-bit block, (i.e., bit ? 0 ? to block 0, bit ? 1 ? to block 1, etc.). program the corresponding bit to ? 0 ? to write-protect the block. for example, program bit 10 to ? 0 ? to write-protect the block 10. the initial value (default) of block 2 is ? fffffffd ?. this means block 1 (tag id) is write-protected before shipping to customer. write protection is a one way process, (i.e., once a block is write-protected, it cannot be modified). it should be noted that the write-protect block itself can be write-protected. tf and fr bits in block 0 are not write-protectable, even if th e write protection bit in the block is set. table 7-10: write-protect 7.3.4 blocks 3 - 5: fast read fields these blocks contain data bits for the fr response. the state of the df bits (see table 7-6) in block 0 determines the actual number of bits to be sent. this block can be used both as a customer id and as additional tag id numbers. these blocks are called fast read field (frf) because the device sends the frf data immediately following the frr command only (itf mode), or as soon as energized (ttf mode), without an additional bl ock read command. this means that the reading of this frf data can be done by frr command only. read ing of other block data requires the frr and block read commands. only the frr device (fr bit = set) outputs the frf data. the frb device (fr bit = cleared) does not send the frf data. mt1 mt0 memory type 00 single level eeprom (default). 01 reserved for future uses (e.g., multi level eeprom). 10 reserved for future uses. 11 reserved for future uses. note: the mt bits are ?hardwired?. tm2 tm1 tm0 total memory size 00 0 512 bits 00 1 1 kbit (default) 01 0 tbd 01 1 tbd 10 0 tbd 10 1 tbd 11 0 tbd 11 1 tbd note: the tm bits are ?hardwired?. b0:(20-0) available for user block x write status bit x of write-protect block block x writable 1 block x write-protected 0
? 2003 microchip technology inc. ds40232h-page 35 MCRF450/451/452/455 8.0 device testing the device will be shipped to customers with the fr bit set, and with block 1 write-protected. the following bits are factory programmed prior to shipping: 1. df0 (b0:26) and df1(b0:27) are set to ? 0 ?s. 2. tft0 (b0:28) and tft1(b0:29) bits are set to ? 1 ?s. 3. all bits in the fr field (blocks 3-5) are programmed to ? 1 ?s. 4. failed device in the te st mode: (1) tag id is programmed with "bad badba" and (2) inked with black color on the die (see section 10.0 ?failed die identification? , for the failed die identification).
MCRF450/451/452/455 ds40232h-page 36 ? 2003 microchip technology inc. 9.0 examples example 9-1: read/write pulse sequence t to write 1 block (32 bits) in norma l mode with ts = 1: ~ 78.014 ms to read 1 block (32 bits) in normal mode with ts = 1: ~ 42.214 ms frr or frb command (5 gap pulses = 1.575 ms) interrogator command tag response (fr response) interrogator command (mc and read/write) tag response (to read/write) interrogator command (end process) tag response to end process for frr response: (preamble (8 bits) + tc (3 bits) + tp (4 bits) + ? 0 ? + 32 bits of tag id + frf (32-96 bits) + ccrc of tag id and frf data = 160 bits max = 2.286 ms) for frb response: (preamble (8 bits) + ? 00001 ? + ? 000 ? + 32-bit tag id (block 1 data) = 64 bits = 0.914 ms) listening window (t lw ) for 1 ms t t decode (1.225 ms) time slot (ts) matching code during listening window: mc code = calibration pulse (1 sym bol) + matched tag id (8 bits) + mc code type (3 bits) + 1 parity bit = cal. pulse (1 symbol) + 12 bits = 4 symbols = 11.2 ms t for reading: cal. pulse (1 symbol) + read command (msn first) + address (msn first + parity) = cal. pulse + 3 symbols = 11.2 ms for writing: cal. pulse (1 sym bol) + write command (msn first) + address (msn first) + data (lsn first) + parity/crc (lsn first) = cal. pulse (1 symbol) + 14 symbols = 42 ms twrite for eeprom (5 ms) t device outputs: after a completion of write cycle: preamble (8 bits) + written block # (5 bits) + ? 000 ? + written block data (32 bits) + ccrc/scrc (16 bits) = 64 bits = 0.914 ms after read command: preamble (8 bits) + block # (5 bits) + ? 000 ? + block data (32 bits) + ccrc/scrc (16 bits) = 64 bits = 0.914 ms t t end process command: cal. pulse + end process command (? 111 ?) + address (? 01010 ?) + parity (1) = cal. pulse + 3 symbols = 11.2 ms device response: 8-bit preamble (? 11111110 ?) (0.114 ms) (frr or frb) + scrc (16 bits)
? 2003 microchip technology inc. ds40232h-page 37 MCRF450/451/452/455 example 9-2: calculation of matching code for tag id = 825fe1a0 (hex, msb first) the ?match? part of the matching code is calcula ted by the bit-wise equation in equation 6-2: ?match (8 bits)? = tag id bit range a:b = {4 (tc)}modulo 32: {4(tc + 1) + 3} modulo 32 for tc = 2, the above equati on gives a = 8, and b = 15. the ?match (8 bits)? is chosen from (8th 9th 10th 11th) and (12th 13th 14th 15th) bits of the tag id. therefore, for the tag id = 825fe1a0 (hex) = b/1000 0010 0101 1111 1110 0001 1010 0000/, ?match (8 bits)? = b/1110 0001/ = 1e (hex). using this ?match? part, a complete se t of matching code is assembled as: 1e5 for mc1, and 1e9 for mc2 where: 5 in the mc1 was from b/0101/ ( 010 for mc1 and the last ? 1 ? is a parity bit), 9 in the mc2 was from b/1001/ ( 100 for mc2 and the last ? 1 ? is a parity bit). gap position in the 1-of-16 ppm signal for the calculated mc codes: the gap position numbers in the 1-of-16 ppm for the calc ulated mc codes are (see figure 6-9 for 1-of-16 ppm): positions 1, 14, and 5 for 1e5 for mc1 code positions 1, 14, and 9 for 1e9 for mc2 code. the ?match? part of the matching code for various tcs are given in table 9-1. table 9-1: calculated ?match? for tag id = 825fe1a0 (hex) tc ?match (8 bits) in hex? 00a 1a1 21e 3ef 4f5 552 628 780
MCRF450/451/452/455 ds40232h-page 38 ? 2003 microchip technology inc. example 9-3: to write data into the device the interrogator command structure for writing (see section 6.2.1 ?structure of read/ write command signals? ) is: calibration pulse + writing command (msn first) + address (msn first) + data (lsn first) + parity/crc (lsn first) if the interrogator wants to write data ?0123cdef (hex, msb to lsb)? to block 5, the following message will be sent: calibration pulse + write command (msn fi rst) + address (msn first) + data (lsn first) + parity/crc (lsn first) = cal. pulse + 101 (write command) + 00101 (address) + f e d c 3 2 1 0 (data, hex) + crc = calibration pulse + a 5 f e d c 3 2 1 0 6 0 2 e (hex string) the hex string above is encoded with the 1-of-16 ppm signals. see figure 6-10 for th e 1-of-16 ppm representation of hex values. referring to figure 6-10, the gap positions in the 1-of-16 ppm for th e above hex string are: positions 10 (a), 5 (5), 15 (f), 14 (e), 13 (d), 12 (c), 3 (3), 2 (2), 1 (1), 0 (0), 6 (6), 0 (0), 2 (2), e (14). device response: 1. if writing is completed: the device sends the wr itten data after 5 msec of eeprom writing time. 2. if writing is failed due to insufficie nt programming voltage for unprotected block: the de vice sends the current block data after about 500 sec of delay. 3. if writing is failed because the bloc k is write-protected block: the device sends the current block data immediately after the command. 4. if writing is failed due to incorrect crc: the device does not respond at all. figure 9-1: flow chart for the device response to the write command note: crc = crc for the write command, a ddress, and data. calibration pulse is not included for the crc calculation. see application note an752 (d s00752) for the crc calculation algorithm. wait for command received write command? is crc correct? read and send block data eeprom start high voltage and wait for about 500 sec have sufficient write eeprom data (5 msec) yes no yes yes yes no no no is the block write-protected? programming? high voltage for
? 2003 microchip technology inc. ds40232h-page 39 MCRF450/451/452/455 example 9-4: to read data from the device to read the content of block 5 that has been programmed in the previous example, the interrogator sends the following command: calibration pulse + read command (? 110 ?) + address (? 00101 ?) + parity (? 0 ?) = calibration pulse + c50 (hex) the gap positions in the 1-of-16 ppm signal for the above hex string are: 12 (c), 5 (5), 0 (0). device response: when the device receives the above interrogator command, the device outputs the following 70 khz manchester encoded data string (see section 6.2.2 ?structure of device response? ): preamble (8 bits) + block number (5 bi ts, lsb first) + ?000? + block data (32 bits, lsb first) + scrc (16 bits) = 1-1-1-1-1-1-1-0 (f7) + 1-0-1-0-0-0-0-0 (5 0) + 1-1-1-1 0-1-1-1 1-0-1-1... 1-0-0-0 0-0-0-0 (f e d c 3 2 1 0) + 0-1-1-0 0-0-0- 0 0-1-0-0 0-1-1-1 (602e). example 9-5: to send the ?end process? command the interrogator command structure (see section 6.2 ?anti-collision command controller? ) for the end process is: calibration pulse + end process command (? 111 ?) + address (? 01010 ?) + parity ( 1 ) = calibration pulse + ea1 (hex) the gap positions in the 1-of-16 pp m signal for the above hex string are: 14 (e), 10 (a), 1 (1). device response: the device outputs the 8-bit preamble (? 11111110 ?) when it receives the end pr ocess command, and enters the sleeping loop.
MCRF450/451/452/455 ds40232h-page 40 ? 2003 microchip technology inc. 10.0 failed die identification every die on the wafer is elec trically tested according to the data sheet specifica tions and visually inspected to detect any mechanical da mage, such as mechanical cracks and scratches. any failed die in the test or visual inspection is identified by black colored ink. ther efore, any die covered with black ink should not be used. the ink dot specification: ink dot size: 254 m in circular diameter position: central third of die color: black 11.0 wafer delivery documentation the wafer is shipped with the following information: microchip technology inc. mp code lot number total number of wafers in the container total number of good dice in the container average die per wafer (dpw) scribe number of wafers with number of good dice 12.0 notice on die and wafer handling the device is very susceptible to electrostatic discharge (esd), which can cause a critical damage to the device. special attentio n is needed during the handling process. any ultraviolet (uv) light can erase the memory cell contents of an unpackaged device. fluorescent lights and sunlight can also eras e the memory cell, although it takes more time than uv lamps. therefore, keep any unpackaged device out of uv light and also avoid direct exposure of strong fluorescent lights and shining sunlight. certain ic manufacturing, cob, and tag assembly operations may use uv light. operations such as back- grind de-tape, certain clea ning procedures, epoxy or glue cure should be done without exposing the die surface to uv light. using x-ray for die inspection will not harm the die, nor erase memory cell contents. 13.0 references it is recommended that t he reader reference the following documents. 1. ? antenna circuit design for rfid applications ?, an710, ds00710. 2. ? rfid tag and cob development guide with microchip?s rfid devices ?, an830, ds00830. 3. ? crc algorithm for mcrf45x read/write devices ?, an752, ds00752. 4. ? interface control document for 13.56 mhz anti-collision interrogator ?, an759, ds00759. 5. ? 13.56 mhz reader reference design for the MCRF450/451/452/455 read/write devices ?, ds21654.
? 2003 microchip technology inc. ds40232h-page 41 MCRF450/451/452/455 14.0 packaging information 14.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn MCRF450 237 0025 legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line thus li miting the number of available characters for customer specific information. * standard device markin g consists of microchip part number, year code, week code, and traceability code. for device marking beyond this, cert ain price adders apply. please check with your microchip sales office. for qtp devices, any special ma rking adders are included in qtp price. MCRF450 0025 237
MCRF450/451/452/455 ds40232h-page 42 ? 2003 microchip technology inc. package marking information (continued) legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line thus li miting the number of available characters for customer specific information. * standard device markin g consists of microchip part number, year code, week code, and traceability code. for device marking beyond this, cert ain price adders apply. please check with your microchip sales office. for qtp devices, any special ma rking adders are included in qtp price. mcrf45x cob 6 . 2 7 3 5 . 0 0 3 1 . 8 4 1 . 0 6 1. 85 9 . 6 5 r0.20(4 x) 2. 375 3 . 7 5 5 . 9 0 9 . 6 5 2 . 5 2 ? 2.00 5. 60 1. 94 4. 75 9 . 6 5 9 . 6 5 note 2 9 . 6 5 1. 42 1. 42 9. 50 4. 75 5 . 2 1 1. 58 0. 40 9. 50 4. 23 4. 90 5. 00 0 . 6 0 ( 2 x ) 0.80(2 x) r1.3 0 3. 88 8 . 0 0 1 . 5 3 ( 4 x ) 0.60(4 x) r0.16 (2 x) r0.2 0 5 . 1 0 6 . 8 8 0.30 (ref .) 1 . 5 0 0.40 (max.) note : 1. reject hole by device testing 2. top gate mark (option) 3. total package thickness excludes punching burr 9.50 x y detail x
? 2003 microchip technology inc. ds40232h-page 43 MCRF450/451/452/455 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flas h or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
MCRF450/451/452/455 ds40232h-page 44 ? 2003 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions . mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2003 microchip technology inc. ds40232h-page 45 MCRF450/451/452/455 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may downlo ad files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a variety of microchip spe cific business information is also available, including li stings of microchip sales offices, distributors and fa ctory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of th e latest versions of all of microchip's development systems software products. plus, this line provides in formation on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. an d most of canada, and 1-480-792-7302 for the rest of the world. 042003
MCRF450/451/452/455 ds40232h-page 46 ? 2003 microchip technology inc. reader response it is our intention to provide yo u with the best documentation possible to en sure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter , and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us wi th your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _ ________ - _________ ds40232h MCRF450/451/452/455 1. what are the best features of this document? 2. how does this document meet your ha rdware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or mislead ing information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. ds40232h-page47 MCRF450/451/452/455 product identification system to order or obtain information, e.g., on pricing or deliver y, refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literatu re center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon a nd data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: MCRF450: 13.56 mhz anti-collision read/write microid device w/no internal resonant capacitor MCRF450/7m: cob (chip-on-board) module with dual 68 pf capacitor mcrf451: 13.56 mhz anti-collision read/write microid device w/100 pf internal resonant capacitor mcrf452: 13.56 mhz anti-collision read/write microid device w/25 pf internal resonant capacitor mcrf455: 13.56 mhz anti-collision read/write microid device w/50 pf internal resonant capacitor temperature range: = -20 c to +70 c package: wf = sawed 8" wafe r on frame (8 mil backgrind) wfb = bumped, sawed 8" wafer on frame (8 mil backgrind w = 8" wafer (11 mil backgrind) wb = bumped 8" wafer (8 mil backgrind) s = dice in waffle pack (8 mil backgrind) sb = bumped die in waffle pack (8 mil backgrind) x/sn = soic (150 mil body), 8-lead (rotated pinout) p = pdip (300 mil body), 8-lead examples: a) MCRF450/w: 13.56 mhz anti-collision read/write microid device, 1 kbit, no cap, 8" wafer, 11-mil backgrind. b) MCRF450/7m: 13.56 mhz anti-collision read/write microid cob (ist ioa2), 1 kbit, 68 pf dual capacitor between antenna a and b, antenna b and v ss . thickness = 0.4 mm. c) mcrf451/wf: 13.56 mhz anti-collision read/write microid device, 1 kbit, 100 pf internal res cap, 8" wafer on frame, 8 mil backgrind. d) mcrf451/s: 13.56 mhz anti-collision read/write microid device in waffle pack, 1 kbit, 100 pf internal res cap, 8-mil thickness. e) mcrf452/wfb: 13.56 mhz anti-collision read/write microid bumped device for flip- chip assembly, 1 kbit, 50 pf dual (25 pf) internal res cap, bumped 8" wafer, 8-mil backgrind wafer on frame. f) mcrf455x/sn: 13.56 mhz anti-collision read/write microid device in soic package, 1k bit, 50 pf internal res cap.
MCRF450/451/452/455 ds40232h-page 48 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds40232h-page 49 information contained in this publication regarding device applications and the like is in tended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual pr operty rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. accuron, application maestro, dspicdem, dspicdem.net, ecan, econom onitor, fans ense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the cod e protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improving the code protection features of our products. attempts to break micro chip?s code protection feature may be a violation of the digita l millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted wo rk, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial ee proms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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